The search for faster, more efficient memory circuits is a constant goal in the ever progressing semiconductor market. Video Random Access Memory (VRAM) circuits outperform similar Dynamic Random Access Memory (DRAM) circuits for a variety of applications. This is due in part to an independent static memory, identified as a Serial Access Memory (SAM), incorporated in conjunction with a DRAM in the VRAM.
In a VRAM, data is capable of being transferred between the DRAM and SAM as necessary. Data transferred from the DRAM to the SAM is considered a read transfer, and data transferred from the SAM to the DRAM is a write transfer. Moreover, to use the SAM as a serial output port, the SAM is addressed in an incremental manner by an address counter/pointer, making it well suited for high speed sequential data streams.
A VRAM is advantageous over a DRAM, for example, because the VRAM increases the bandwidth of raster graphic display frame buffers. Namely, VRAM-based buffers give a Cathode Ray Tube (CRT) driver circuitry access to pixel data from the SAM port, alleviating any DRAM-port contention problem, and thus improving screen redraw performance when changing display information. DRAM-port access remains available to a graphics controller or coprocessor while screen refresh data is constantly supplied, independently, by the SAM port.
Although the VRAM offers its advantages, it retains a drawback in effectuating a Real-Time Read Transfer (RTRT) of data. For example, when display data needs to be changed immediately during a current refresh cycle of the CRT, the actual transfer of data must take place within one serial clock cycle (the cycle between the positive edge for the last piece of "old" data and the positive edge for the first piece of "new" data).
In order to speed up a Real-Time Read Transfer, circuitry has been developed in the prior art to pre-load the serial port buffer with a first bit of new data substantially simultaneously with the transfer of the rest of the data from DRAM to SAM which is to be serially output following the first bit. Details on this method of pre-loading the serial port are disclosed in U.S. patent application Ser. No. 07/701,470, entitled Pipelined SAM Register Serial Output, filed May 15, 1991, and assigned to Micron Technology, Inc.
Although the aforementioned application discloses a method of pre-loading the serial read pipe (i.e., a serial port having a buffer), it also retains a drawback. Namely, the timing involved in the steps for pre-loading the serial port mandate that the serial clock cycle be no less than about 50 nanoseconds (ns).
Given the continuous effort to increase speeds in the semiconductor and computing industries, a clock cycle of 50 ns is an undesirable limitation. Accordingly, objects of the present invention are to provide an improved memory circuit and method for pre-loading a serial port pipe with significantly improved clock cycle performance for Real-Time Read Transfers.